In recent years, the computer industry has experienced extremely rapid growth in all aspects, including the number of units produced, breadth of applications, power and speed of operation, and complexity of computing machines. The last aspect has created significant challenges for designers and developers of the integrated circuit devices that lie at the heart of a computing machine. Each such device must be able to complete more tasks, of increasing complexity, in a smaller volume. These demands have led to the marriage of large scale integrated (LSI) devices, each containing thousands of transistors and other functional elements, with interconnecting wiring structures that are built into the packages for the LSI devices.
The wiring structures must provide three types of electrical connections. They must connect functional elements within an LSI device, where the physical locations of those elements and the topology of the various connections preclude the possibility of accomplishing the connection within the LSI device itself They must also provide connections between two or more LSI devices that are built into a single functional device. They must also connect an LSI device to other devices used in a computer, such as circuit boards and other LSI devices.
The increasing complexity and size of LSI devices used in high-end servers has placed similar requirements on wiring structures; they have become larger and more complex. As the size of the wiring structures has increased, so has the probability that any particular wiring structure might contain a manufacturing defect that would either require repair or render the wiring structure useless. The goal of achieving a cost-effective yield of acceptable parts has become a significant issue in the manufacture of such devices.
A particular form of thin film wiring structure, termed a "plane pair" thin-film structure, has achieved widespread usage in the industry, for it affords considerable design flexibility and reasonable manufacturing costs and yield. FIG. 1 illustrates a conventional plane pair thin-film structure in cross section. See Microelectronics Packaging Handbook, page 697 (edited by R. Tummala & E. Rymaszewski eds., published by Van Nostrand Reinhold, 1989). The plane pair thin-film structure 1 begins with a silicon or ceramic substrate 2. The structure then comprises four electrically conducting layers separated from each other by (typically polyimide) insulating layers 7. In order, the conducting layers comprise a ground or reference plane layer 3, a "y" wiring or signal layer 4, an "x" wiring or signal layer 5, and a second reference plane layer 6. A top surface metallization or terminal metal 8 is provided on top of plane pair thin-film structure 1. The reference plane layers 3, 6, which may be mesh-like in configuration, serve important electrical functions including shielding, controlling signal parameters, and distributing power and ground potentials to various parts of the LSI device. The signal layers 4, 5 are comprised of a large number of parallel ribbons that carry the signals representing the functionality of the LSI device.
Plane pair thin-film structure 1 shown in FIG. 1 is typically constructed by fabricating each layer, in sequence, starting with substrate 2. Connections between adjacent conducting layers are achieved by connectors that pass through holes in the intervening insulating layer; these connectors are termed "vias." Where appropriate, a section of a conducting layer may be electrically isolated from the remainder of the layer to facilitate connection of vias between nonadjacent conducting layers. Additional insulating layers outside the reference plane layers are typically included in the design of a plane pair thin-film structure.
The increasing complexity of wiring structures has led to stacking additional insulating and conducting layers on top of a plane pair thin-film structure, just to achieve the required number of electrical connections within the topological constraints of the physical locations of the elements being connected. Such a structure meets the requirements of certain applications for higher wiring density to interconnect semiconductor chips. FIG. 2 illustrates a cross section through a conventional multiple-plane pair thin-film structure 10. See "Multilevel Thin-Film Package in Use NEC-SX3," NEC Corporation (Japan) (April 1990). Essentially, a second plane pair thin-film structure is formed in serial fashion on top of a first plane pair thin-film structure.
More specifically, a ceramic base substrate 11 with power and ground planes 13 is provided. Input-output pins 12 extend from substrate 11. Over the connection point 14 is formed the two plane pair structure 15. In sequential order, two plane pair structure 15 comprises a ground or reference plane layer 3, an "x" wiring or signal layer 5, a "y" wiring or signal layer 4, a second reference plane layer 6, a second "x" wiring or signal layer 16, a second "y" wiring or signal layer 17, and a third reference plane layer 18. A terminal metal 8 is provided on top of two plane pair structure 15. Also illustrated in FIG. 2 are a flip tab carrier 18 and ground 19.
Two plane pair structure 15 has a number of disadvantages. First, the problem of achieving a cost-effective yield with such stacked wiring structures is more severe than for single plane pair thin-film structures. Because all of the layers are built sequentially, even one defect in one layer renders the entire structure electrically defective. Most defects occur in the signal layers and, because the four signal layers are built sequentially, the over-all yield of the manufacturing process tends to be low. This yield problem is exacerbated if six or more signal layers are required for the interconnection density.
The sequential construction of the various layers also causes a second disadvantage of two plane pair structure 15: the total manufacturing cycle time is long. In fact, the cycle time is practically not economical. Finally, the conventional two plane pair structure 15 does not allow reference planes with different potential to be adjacent. This disadvantage precludes two plane pair structure 15 from having efficient low inductance paths to decoupling capacitors.
Some of the methods used to produce thin-film structures are taught in U.S. Pat. Nos. 5,258,236, No. 5,534,094, and No. 5,534,466. All three of these patents are assigned to the assignee of the present invention. The teachings of these three patents are incorporated in this application by reference.
Titled "Multilayer Thin Film Structure And Parallel Processing Method For Fabricating Same," U.S. Pat. No. 5,258,236 discloses a method and apparatus for releasing a workpiece from a substrate. The method includes providing a substrate which is transparent to a predetermined wavelength of electromagnetic radiation; forming, on the substrate, a separation layer which degrades in response to the predetermined radiation; providing the workpiece on the separation layer; and directing the predetermined radiation at the separation layer through the transparent substrate so as to degrade the separation layer and to separate the workpiece from the substrate.
The application that issued as U.S. Pat. No. 5,534,094 is a continuation of U.S. patent application Ser. No. 08/080,085, filed one Jun. 21, 1993 and later abandoned, which is a divisional of the application (Ser. No. 07/695,368, filed May 3, 1991) that issued as U.S. Pat. No. 5,258,236. The subject matter disclosed by the '094 patent is essentially the same as that disclosed in the '236 patent.
U.S. Pat. No. 5,534,466 is titled "Method Of Making Area Direct Transfer Multilayer Thin Film Structure." The '466 patent discloses a process for transferring a thin film wiring layer to a substrate in the construction of multilayer chip modules. The process initially provides a sacrificial release layer formed on a surface of a carrier. Directly on the release layer there is formed in inverted fashion a plurality of multilevel thin-film structures having at least one wiring path of metallic material exposed on the surface opposite the carrier. An electronic packaging substrate is provided, and solder or other joining material is applied to one or both of the exposed metallic surfaces of the multilevel thin-film structure or the substrate. The multilevel thin-film structure is then joined to the substrate so that the attached carrier is remote from the substrate. The release layer is subsequently contacted with an etchant for the release layer so as to remove the carrier from the multilevel thin-film structure to produce a multilayer chip module.
Of course, other patents exist that teach methods used to produce thin-film structures. U.S. Pat. No. 4,812,191 is titled "Method Of Forming A Multilevel Interconnection Device." The '191 patent discloses a method of fabricating a high density electrical interconnection member by forming a composite interconnection from metallic conductors on cured liquid polymer resin on a substrate. The resin is cured at an elevated temperature to form a solid dielectric layer. Successive metallic and dielectric layers form an interconnection subassembly with the coefficient of thermal expansion of the substrate being less than the subassembly. The temperature of the subassembly is lowered placing it in tension. A support member is adhered to the exposed surface of the subassembly and the substrate is removed. Multiple subassemblies can be joined together physically and electrically to form a complex device for interconnecting a plurality of integrated circuit chips for high performance computer applications.
The deficiencies of the conventional methods used to produce multilayer thin-film structures show that a need still exists for an improved process of manufacture. To overcome the shortcomings of the conventional methods, a new process is provided. An object of the present invention to provide an improved thin-film structure that can be produced economically with a high yield of acceptable structures. It is also an object of the present invention to provide a thin film wiring structure that can accommodate the design requirements of high-end servers, applications for which prior art structures are inadequate. It is another object of the present invention to provide a multiple-plane pair thin-film structure that is manufactured in modular fashion, such that each module can be tested for conformity to applicable specifications before assembly into the complete structure.
It is a further object of the present invention to provide a process, for manufacturing such multiple-plane pair thin-film structures, characterized by higher yield of acceptable products than conventional methods. It is yet another object of the present invention to provide a process for manufacturing such multiple-plane pair thin-film structures such that the time required to complete the manufacturing process is less than that required by prior art methods. Still other objects and advantages of the present invention will be apparent from the description of the invention provided in this specification.